DCM module VHDL code - Revision history

Joosteto at 16:49, 26 May 2013

2013-05-26T16:49:03Z

2013-04-26T11:22:13Z

2013-04-25T22:20:13Z

2013-04-23T22:11:20Z

2013-04-23T22:01:26Z

2013-04-22T18:57:26Z

2013-04-22T18:57:02Z

2013-04-22T18:47:19Z

2013-04-22T18:46:14Z

2013-04-21T22:54:19Z

← Older revision		Revision as of 16:49, 26 May 2013
Line 1:		Line 1:
	With the following 3 files (the DCM part is generated by the IPCoreGen of Xilinx), the DCM module can be made to work without the having to run the IP CORE generator.		With the following 3 files (the DCM part is generated by the IPCoreGen of Xilinx), the DCM module can be made to work without the having to run the IP CORE generator.
		+
		+	Similar code can also be found in: Edit/Language Templates..., and then select Spartan 3, Clock Components, Clock MUX.

	Top level <tt>LEDtest.vhdl</tt>:		Top level <tt>LEDtest.vhdl</tt>:

@@ Line 163: / Line 163: @@
 And the constraints.ucf file:
  <nowiki># Crystal Clock - use 32MHz onboard oscillator
-NET "clk_in" LOC = "P89" | IOSTANDARD = LVCMOS25 | PERIOD = 31.25ns ;
+NET "clk_in" LOC = "P89" | IOSTANDARD = LVCMOS25 | PERIOD = 50.0ns ;
 # Wing1 Column A

@@ Line 161: / Line 161: @@
 end BEHAVIORAL;</nowiki>
-And the contraints.ucf file:
+And the constraints.ucf file:
  <nowiki># Crystal Clock - use 32MHz onboard oscillator
-NET "clk_in" LOC = "P89" | IOSTANDARD = LVCMOS25 | PERIOD = 50.0ns ;
+NET "clk_in" LOC = "P89" | IOSTANDARD = LVCMOS25 | PERIOD = 31.25ns ;
 # Wing1 Column A

@@ Line 282: / Line 282: @@
 =See Also=
 * [[Spartan 3E]]
 * [[FPGA]]

@@ Line 78: / Line 78: @@
 --  \___\/\___\
 --
 --Design Name: DCM71
 --Device: xc3s500e-4vq100
@@ Line 85: / Line 84: @@
 -- Generated by Xilinx Architecture Wizard
 -- Written for synthesis tool: XST
 library ieee;

@@ Line 149: / Line 149: @@
                 PSINCDEC=>GND_BIT,
                 --RST=>RST_IN,
-					 RST=>GND_BIT,
+		RST=>GND_BIT,
                 CLKDV=>open,
                 CLKFX=>CLKFX_BUF,
@@ Line 162: / Line 162: @@
                 PSDONE=>open,
                 STATUS=>open);
 end BEHAVIORAL;</nowiki>

@@ Line 25: / Line 25: @@
     end component;
-    signal count: integer range 0 to 32000000 := 0;
+    signal count: integer range 0 to 114285719 := 0;
 	 signal clk: std_logic;
 	 signal clk0: std_logic;
@@ Line 49: / Line 49: @@
 		  end if;
 		  LED2<=tmp(0);
-		  if count=31999999 then
+		  if count>=114285714 then
 		    count<=0;
 			 sec<=sec+1;
@@ Line 55: / Line 55: @@
 			 if sec=9 then
 			   sec<=0;
-				duration<=16000000;
+				duration<=32000000;
 			 else
-			   duration<=10000000;
+			   duration<=1000000;
 			 end if;
 		  end if;

← Older revision		Revision as of 18:47, 22 April 2013
Line 284:		Line 284:
	INST DCM_SP_INST PHASE_SHIFT = 0;		INST DCM_SP_INST PHASE_SHIFT = 0;
	INST DCM_SP_INST STARTUP_WAIT = FALSE;</nowiki>		INST DCM_SP_INST STARTUP_WAIT = FALSE;</nowiki>
		+
		+	=See Also=
		+	* [[Spartan 3E]]
		+	* [[FPGA]]

← Older revision		Revision as of 18:46, 22 April 2013
Line 1:		Line 1:
−	With the following 3 files, the DCM module can be made to work without the IP CORE generator.	+	With the following 3 files (the DCM part is generated by the IPCoreGen of Xilinx), the DCM module can be made to work without the having to run the IP CORE generator.

	Top level <tt>LEDtest.vhdl</tt>:		Top level <tt>LEDtest.vhdl</tt>:

@@ Line 64: / Line 64: @@
 end BEHAVIOUR;</nowiki>
-The DCM71.vhdl file (I call it '71' as it's supposed to convert a 25MHz clock into 71.428...MHz):
+The DCM71.vhdl file (I call it '71' as it's supposed to convert a 20MHz clock into 71.428...MHz):
  <nowiki>--------------------------------------------------------------------------------
 -- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
@@ Line 167: / Line 167: @@
 And the contraints.ucf file:
  <nowiki># Crystal Clock - use 32MHz onboard oscillator
-NET "clk_in" LOC = "P89" | IOSTANDARD = LVCMOS25 | PERIOD = 31.25ns ;
+NET "clk_in" LOC = "P89" | IOSTANDARD = LVCMOS25 | PERIOD = 50.0ns ;
 # Wing1 Column A