DX TM1638 Display - Revision history

Joosteto: /* File design_top.vhdl */

2013-05-20T16:17:42Z

File design_top.vhdl

Joosteto: /* File dx_display_xmit.vhdl */

2013-05-20T16:14:36Z

File dx_display_xmit.vhdl

Joosteto: /* File dx_display_xmit.vhdl */

2013-05-20T16:14:02Z

File dx_display_xmit.vhdl

Joosteto: /* File dx_display.vhdl */

2013-05-20T16:13:17Z

File dx_display.vhdl

Joosteto: /* File design_top.vhdl */

2013-05-20T16:12:46Z

File design_top.vhdl

Joosteto: /* File design_top.vhdl */

2013-05-19T20:51:09Z

File design_top.vhdl

Joosteto: /* VHDL code for numeric data display */

2013-05-19T20:40:45Z

VHDL code for numeric data display

Joosteto: /* Commands */

2013-05-19T20:37:54Z

Commands

Joosteto: /* VHDL code for numeric data display */

2013-05-19T20:33:33Z

VHDL code for numeric data display

Show changes

Joosteto: /* Commands */

2013-05-03T08:14:19Z

Commands

@@ Line 73: / Line 73: @@
 --
 --
 ----------------------------------------------------------------------------------
 library IEEE;

@@ Line 484: / Line 484: @@
     --11515/9563=1.204120046010666; log(16)/log(10) = 1.2041199826559246
-    variable bcd : unsigned((11515*(bin'left+1))/9563-1 downto 0) := (others => '0');
+    --(11515*i+9563*4-1)/(9563*4)*4
     variable bint : bitarray(bin'range):=bin;
     variable i : integer:=0;
@@ Line 500: / Line 501: @@
     return bcd;
   end to_bcd;
-end package body;</nowiki>
+end package body;
 =See Also=

@@ Line 343: / Line 343: @@
 entity dx_display_xmit is
   Port (
     clk      : in  STD_LOGIC;
@@ Line 354: / Line 355: @@
     d_strobe : out STD_LOGIC;
     d_clk    : out STD_LOGIC;
-    d_data   : inout STD_LOGIC
+    d_data   : inout STD_LOGIC);
 end dx_display_xmit;
@@ Line 363: / Line 362: @@
   signal bitsLeftToSend : std_logic_vector(6 downto 0)  := (others => '0');
   signal state          : std_logic_vector(3 downto 0)  := (others => '0');
-  --signal divider        : integer range 0 downto 2048 := 0;
+  signal divider        : integer range 0 to 1023 := 0;
   signal keydataLocal   : std_logic_vector(keydata'range);
 begin
@@ Line 370: / Line 368: @@
   begin
     if rising_edge(clk) then
-      --divider <= divider +1;
+      divider <= divider +1;
       adv      <= '0';
       if reset = '1'  then
         thisByte   <= (others => '0');
         state      <= (others => '0');
         d_strobe <= '1';
         d_clk    <= '1';
         d_data   <= '1';
-        --divider  <= 0;
+        divider  <= 0;
-        divider  <= (divider'left=>'1', others =>'0');
+      elsif divider = (clkDivider-1) then
-        --elsif divider = 63 then
+        divider  <= 0;
         d_strobe <= '1';
         d_clk    <= '1';

@@ Line 194: / Line 194: @@
 entity dx_display is
   PORT(
     clk     : IN std_logic;
@@ Line 204: / Line 205: @@
     );
 end dx_display;
 architecture Behavioral of dx_display is
-  signal counter : std_logic_vector(5 downto 0) := (others => '0');
+  signal counter : integer range 0 to 31 :=0;--std_logic_vector(5 downto 0) := (others => '0');
   signal counterPreClk:std_logic:='0';
   signal counterClk: std_logic:='0';
-  signal nextcounter : unsigned(counter'range);
+  signal nextcounter : integer range  0 to 31; --unsigned(counter'range);
   signal byte       : std_logic_vector(7 downto 0);
@@ Line 219: / Line 219: @@
   signal resetCount : integer range 0 to 32*1000*1000 :=1*100-1;
   signal keydataone : std_logic_vector(7 downto 0);
-  constant headersize: integer := 9;
+  constant headersize: integer := 8;
   COMPONENT dx_display_xmit
     Port (
       clk      : in  STD_LOGIC;
@@ Line 236: / Line 237: @@
 begin
-  nextcounter <= unsigned(counter) + 1;
+  --nextcounter <= unsigned(counter) + 1;
-  Inst_dx_display_xmit: dx_display_xmit PORT MAP(
+  Inst_dx_display_xmit: dx_display_xmit
     clk       => clk,
     reset     => reset,
@@ Line 257: / Line 260: @@
       newData<='1';
       case counter is
-        when  "000000" => byte <= x"00"; endCmd <= '1';
+        --when  "000000" => byte <= x"00"; endCmd <= '1';
-        when  "000001" => byte <= x"46"; endCmd <= '0';
+        when  0 => byte <= x"46"; endCmd <= '0';
-        when  "000010" => byte <= x"00"; endCmd <= '0'; send<='0';
+        when  1 => byte <= x"00"; endCmd <= '0'; send<='0';
-        when  "000011" => byte <= x"00"; endCmd <= '0'; send<='0';
+        when  2 => byte <= x"00"; endCmd <= '0'; send<='0';
            keybyte(0)<=keydataone(0);
            keybyte(4)<=keydataone(4);
-        when  "000100" => byte <= x"00"; endCmd <= '0'; send<='0';
+        when  3 => byte <= x"00"; endCmd <= '0'; send<='0';
            keybyte(1)<=keydataone(0);
            keybyte(5)<=keydataone(4);
-        when  "000101" => byte <= x"00"; endCmd <= '1'; send<='0';
+        when  4 => byte <= x"00"; endCmd <= '1'; send<='0';
            keybyte(2)<=keydataone(0);
            keybyte(6)<=keydataone(4);
-        when  "000110" => byte <= x"40"; endCmd <= '1'; -- Set address mode - auto inc
+        when  5 => byte <= x"40"; endCmd <= '1'; -- Set address mode - auto inc
            keybyte(3)<=keydataone(0);
            keybyte(7)<=keydataone(4);
-        when  "000111" => byte <= x"88"; endCmd <= '1';	-- Turn display on, lowest brightness (0)
+        when  6 => byte <= x"88"; endCmd <= '1';	-- Turn display on, lowest brightness (0)
-        when  "001000" => byte <= x"C0"; endCmd <= '0';-- Write at the left display
+        when  7 => byte <= x"C0"; endCmd <= '0';-- Write at the left display
         when  others =>
-          if unsigned(counter) <= 15+headersize then
+          if counter <= 15+headersize then
-            if counter(0)='1' then
+            if to_unsigned(counter,1)(0)='0' then
-              byte<=digits((to_integer(unsigned(counter))-headersize)/2);
+              byte<=digits((counter-headersize)/2);
             else
-              byte<=leds((to_integer(unsigned(counter))-headersize)/2);
+              byte<=leds((counter-headersize)/2);
             end if;
-            if unsigned(counter) < 15+headersize then
+            if counter < 15+headersize then
               endCmd<='0';
             else
@@ Line 299: / Line 302: @@
       counterPreClk<='0';
       if reset = '1' then
-        counter <= "111111";
+        counter <= 31;
-      elsif counter ="111111" then
+      elsif counter =31 then
         counterPreClk<='1';
-        counter <= "000000";
+        counter <= 0;
-      elsif adv = '1' and counter /= "111111" then
+      elsif adv = '1' and counter < 31 then
         counterPreClk<='1';
-        counter <= std_logic_vector(nextcounter);
+        counter <= nextcounter;
       end if;
     end if;
@@ Line 321: / Line 324: @@
         resetCount <=resetCount-1;
       else
-        resetCount<=200*1000;
+        resetCount<=1*100*1000;
         reset<= not reset;
       end if;

@@ Line 74: / Line 74: @@
 --
 --TODO:
 -- check rounding of compile-time divide (bcd function)
 -- clock-division in dx_display_xmit via counter, not 64-bit register.
@@ Line 94: / Line 93: @@
   COMPONENT dx_display
     PORT(
       clk     : IN std_logic;
@@ Line 114: / Line 114: @@
   signal digits: bytearray(0 to 7) := (others => x"00");
   signal leds: bytearray(0 to 7)   := (others => x"00");
-  signal data: integer range -2000000000 to 2000000000 :=0;
+  signal data: integer range -2000000000 to 2000000000 :=0;--20000/3;
   signal tmp: std_logic_vector(31 downto 0);
   signal keybyte: std_logic_vector(7 downto 0);
 begin
   Inst_dx_display: dx_display
     PORT MAP(
       clk      => clk,
@@ Line 132: / Line 134: @@
   Inst_display7seg:display7seg
     PORT MAP(
-      digits => digits(0 to 7),
+      digits => digits(0 to 1),
-      data   => data);
+      data   => key_int);
- -- Inst_display7segDec:display7seg
+  Inst_display7segDec:display7seg
- --   PORT MAP(
+    PORT MAP(
- --     digits => digits(6 to 7),
+      digits => digits(2 to 7),
- --     data   => decdata);
+      data   => decdata);
   reset_proc: process(clk)
@@ Line 146: / Line 148: @@
         Count <=Count-1;
       else
-        Count<=2*1000*1000;
+        Count<=200*1000*1;
         --for i in 0 to 3 loop
         --  tmp(i*8 + 7 downto i*8) <= keydata(i);
@@ Line 156: / Line 159: @@
         --tmp(15 downto 8) <= keydata(2);
         --tmp(7 downto 0) <= keydata(3);
-        tmp(23 downto 0)<=std_logic_vector(to_unsigned(data+1,24));
+        --tmp(23 downto 0)<=std_logic_vector(to_unsigned(data+1,24));
-        tmp(31 downto 24) <= keybyte;
+        --tmp(7 downto 0) <= keybyte;
+        --tmp(23 downto 16) <= keybyte;
         for i in 0 to 7 loop
           leds(i)(0)<=keybyte(i);
           leds(i)(1)<='0';
         end loop;

@@ Line 64: / Line 64: @@
 =VHDL code for numeric data display=
 ==File <tt>design_top.vhdl</tt>==
  <nowiki>---------------------------------------------------------------------------------

@@ Line 60: / Line 60: @@
 |}
-After sending <tt> 46 C0</tt>, the response will be <tt>00</tt> if the left-most key is not pressed, and <tt>02</tt> if the left-most key is pressed.
+After sending <tt> 46</tt> the responce will be 4 bytes, key one is in bit zero (LSB) of the first byte, key two is in bit one of the second byte, etc.
 =VHDL code for numeric data display=