Joosteto at 18:47, 22 February 2014

2014-02-22T18:47:06Z

Joosteto at 15:18, 15 February 2014

2014-02-15T15:18:38Z

Joosteto at 20:39, 12 February 2014

2014-02-12T20:39:15Z

Joosteto at 20:27, 12 February 2014

2014-02-12T20:27:53Z

Show changes

Joosteto at 07:35, 12 February 2014

2014-02-12T07:35:43Z

Joosteto: Created page with "I couldn't find working sample VHDL files on how to make the PLL_ADV in Spartan 6 work. All I could find was [http://permalink.gmane.org/gmane.comp.hardware.opencores.leon-spa..."

2014-02-11T22:09:38Z

Created page with "I couldn't find working sample VHDL files on how to make the PLL_ADV in Spartan 6 work. All I could find was [http://permalink.gmane.org/gmane.comp.hardware.opencores.leon-spa..."

New page

I couldn't find working sample VHDL files on how to make the PLL_ADV in Spartan 6 work.
All I could find was [http://permalink.gmane.org/gmane.comp.hardware.opencores.leon-sparc/15037 this blog post], but that
didn't simulate with CLKFBIN set to GND. So here is a copy that at least simulats for me:
<nowiki>----------------------------------------------------------------------------------
--Copied from http://permalink.gmane.org/gmane.comp.hardware.opencores.leon-sparc/15037
--by Joost Witteveen
--
--Minimal PLL_ADV VHDL files (only simulation tested. Does it work in real too?)
--
----------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;

--For dynamically changing DLL DCM values:
-- http://hamsterworks.co.nz/mediawiki/index.php/FreqSwitch
entity main is
port(
clkin_1: in std_logic;
clkin_2: in std_logic;
clkout_0: out std_logic;
clkout_1: out std_logic;
clkout_2: out std_logic;
sigout: out std_logic
);

end main;

architecture Behavioral of main is
signal gnd : std_logic :='0';
signal reset: std_logic :='1';
signal resetCount: unsigned(2 downto 0):="000";
begin
reset_process: process(clkin_1)
begin
if clkin_1'event and clkin_1='1' then
if resetCount<5 then
resetCount<=resetCount+1;
sigout<='1';
reset<='1';
else
reset<='0';
sigout<='0';
end if;
end if;
end process;
PLL_ADV_inst : PLL_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => 4,
CLKFBOUT_PHASE => 0.0,
CLKIN1_PERIOD => 10.1,
CLKIN2_PERIOD => 10.1,
CLKOUT0_DIVIDE => 1,
CLKOUT0_DUTY_CYCLE => 0.5,
CLKOUT0_PHASE => 0.000000,
CLKOUT1_DIVIDE => 1,
CLKOUT1_DUTY_CYCLE => 0.5,
CLKOUT1_PHASE => 180.000000,
CLKOUT2_DIVIDE => 4,
CLKOUT2_DUTY_CYCLE => 0.5,
CLKOUT2_PHASE => 0.000000,
CLKOUT3_DIVIDE => 4,
CLKOUT3_DUTY_CYCLE => 0.5,
CLKOUT3_PHASE => 180.000000,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.5,
CLKOUT4_PHASE => 0.000000,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.5,
CLKOUT5_PHASE => 0.000000,
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
EN_REL => false,
PLL_PMCD_MODE => false,
REF_JITTER => 0.100,
RESET_ON_LOSS_OF_LOCK => false,
RST_DEASSERT_CLK => "CLKIN1",
CLKOUT0_DESKEW_ADJUST => "NONE",
CLKOUT1_DESKEW_ADJUST => "NONE",
CLKOUT2_DESKEW_ADJUST => "NONE",
CLKOUT3_DESKEW_ADJUST => "NONE",
CLKOUT4_DESKEW_ADJUST => "PPC",
CLKOUT5_DESKEW_ADJUST => "PPC",
CLKFBOUT_DESKEW_ADJUST => "PPC"
)
port map (
CLKFBDCM => open,
CLKFBOUT => open,
CLKOUT0 => clkout_0,
CLKOUT1 => clkout_1,
CLKOUT2 => clkout_2,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUTDCM0 => open,
CLKOUTDCM1 => open,
CLKOUTDCM2 => open,
CLKOUTDCM3 => open,
CLKOUTDCM4 => open,
CLKOUTDCM5 => open,
DO => open,
DRDY => open,
LOCKED => open,
CLKFBIN => clkin_1,
CLKIN1 => clkin_1,
CLKIN2 => gnd, --clkin_1,
CLKINSEL => '1', -- 1 selects CLKIN1, and 0 selects CLKIN2
DADDR => "00000",
DCLK => '0',
DEN => '0',
DI => "0000000000000000",
DWE => '0',
REL => '0',
RST => reset -- Asynchronous PLL reset
);

end Behavioral;
</nowiki>

With the following test bench:

<nowiki>
--
-- VHDL Test Bench Created by ISE for module: main

--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT main
PORT(
clkin_1 : IN std_logic;
clkout_0 : OUT std_logic;
clkout_1 : OUT std_logic;
clkout_2 : OUT std_logic;
sigout : OUT std_logic
);
END COMPONENT;

--Inputs
signal clkin_1 : std_logic := '0';

--Outputs
signal clkout_0 : std_logic;
signal clkout_1 : std_logic;
signal clkout_2 : std_logic;
signal sigout : std_logic;

-- Clock period definitions
constant clkin1_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: main PORT MAP (
clkin_1 => clkin_1,
clkout_0 => clkout_0,
clkout_1 => clkout_1,
clkout_2 => clkout_2,
sigout => sigout
);

-- Clock process definitions
clkin1_process :process
begin
clkin_1 <= '0';
wait for clkin1_period/2;
clkin_1 <= '1';
wait for clkin1_period/2;
end process;

stim_proc: process
begin
wait for 100 ns;
wait;
end process;

END;
</nowiki>

@@ Line 29: / Line 29: @@
 --For dynamically changing DLL DCM values:
 -- http://hamsterworks.co.nz/mediawiki/index.php/FreqSwitch
 entity main is
   port(

@@ Line 59: / Line 59: @@
         CLKFBOUT_MULT         => 10,
         CLKFBOUT_PHASE        => 0.0,
-        CLKIN1_PERIOD         => 10.1,
+        CLKIN1_PERIOD         => 10.0,
-        CLKIN2_PERIOD         => 10.1,
+        CLKIN2_PERIOD         => 10.0,
         CLKOUT0_DIVIDE        => 1,
         CLKOUT0_DUTY_CYCLE    => 0.5,

@@ Line 11: / Line 11: @@
 * With CLKOUT1DIVIDE=1, the CLKOUT1 frequency is 500/10=500MHz
  <nowiki>----------------------------------------------------------------------------------
 --Copied from http://permalink.gmane.org/gmane.comp.hardware.opencores.leon-sparc/15037