Xilinx - Revision history

Joosteto at 17:37, 16 July 2015

2015-07-16T17:37:48Z

2014-02-22T11:12:22Z

ISE WebPACK for Linux notes

2014-02-13T21:45:50Z

ISE WebPACK for Linux notes

2014-02-12T10:20:38Z

Entity port data5 does not match with type unsigned of component port

2014-01-31T15:34:10Z

Entity port data5 does not match with type unsigned of component port

2014-01-31T15:32:02Z

Entity port data5 does not match with type unsigned of component port

2014-01-31T15:06:47Z

Cannot compile generated C files

2013-11-29T22:57:29Z

Cannot compile generated C files

2013-05-23T21:58:20Z

ISE WebPACK for Linux notes

2013-05-23T11:53:45Z

Issues (14.4)

@@ Line 6: / Line 6: @@
 * Xilinx constrants.ucf file info [http://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf Constraints Guide]
 * programming (sending .bit file to FPGA) via [http://xc3sprog.sourceforge.net/hardware.php xc3sprog]?
 =ISE WebPACK for Linux notes=

@@ Line 23: / Line 23: @@
  #Set the env variables:
  INSTALL_DIR=/opt
- VER=14.7
+ VER=14.5
  . $INSTALL_DIR/Xilinx/$VER/ISE_DS/settings32.sh

@@ Line 23: / Line 23: @@
  #Set the env variables:
  INSTALL_DIR=/opt
- . $INSTALL_DIR/Xilinx/14.5/ISE_DS/settings32.sh
+ . $INSTALL_DIR/Xilinx/$VER/ISE_DS/settings32.sh
  #starting the main app:
- $INSTALL_DIR/Xilinx/14.5/ISE_DS/ISE/bin/lin/ise
+ $INSTALL_DIR/Xilinx/$VER/ISE_DS/ISE/bin/lin/ise
  #starting coregen:
- $INSTALL_DIR/Xilinx/14.5/ISE_DS/ISE/bin/lin/coregen
+ $INSTALL_DIR/Xilinx/$VER/ISE_DS/ISE/bin/lin/coregen
 ==Issues (14.4)==
 * When first starting <tt>ise</tt>, it will ask for a license by starting a browser (chromium on my system). But as it sets the LD_LIBRARY_PATH variable to Xilinx-compiles stdc++ library, chromium-browser cannot start start. As the licence manager doesn't inform the user of the crashed browser, simply nothing happens after clikcing the 'get licence' (or whatever it was called) button. I fixed this with:

@@ Line 98: / Line 98: @@
 =Entity port data5 does not match with type unsigned of component port=
 They do match, but somehow Xilinx 14.5 doesn't like it. Looks like issue [http://www.xilinx.com/support/answers/33877.htm 33877], but that was for 11.4 (and the proposed solution doesn't work, I did try).
 The complaint happens in the "Synthesize XST" phase ("View RTL Schematic").

@@ Line 98: / Line 98: @@
 =Entity port data5 does not match with type unsigned of component port=
 They do match, but somehow Xilinx 14.5 doesn't like it. Looks like issue [http://www.xilinx.com/support/answers/33877.htm 33877], but that was for 11.4 (and the proposed solution doesn't work, I did try).
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;
@@ Line 115: / Line 119: @@
 end Behavioral;</nowiki>
-And the following commands.vhdl file: <nowiki>library IEEE;
+And the following commands.vhdl file:
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.NUMERIC_STD.ALL;

← Older revision		Revision as of 15:32, 31 January 2014
Line 98:		Line 98:
	=Entity port data5 does not match with type unsigned of component port=		=Entity port data5 does not match with type unsigned of component port=
	They do match, but somehow Xilinx 14.5 doesn't like it. Looks like issue [http://www.xilinx.com/support/answers/33877.htm 33877], but that was for 11.4 (and the proposed solution doesn't work, I did try).		They do match, but somehow Xilinx 14.5 doesn't like it. Looks like issue [http://www.xilinx.com/support/answers/33877.htm 33877], but that was for 11.4 (and the proposed solution doesn't work, I did try).
		+	With the following main.vhdl file <nowiki>library IEEE;
		+	use IEEE.STD_LOGIC_1164.ALL;
		+	use IEEE.NUMERIC_STD.ALL;
		+
		+	entity commands is
		+	port (
		+	count:in unsigned (63 downto 0);
		+	data1: inout unsigned (63 downto 0)
		+	);
		+	end commands;
		+
		+	architecture Behavioral of commands is
		+
		+	begin
		+	data1<=count +1;
		+	end Behavioral;</nowiki>
		+
		+	And the following commands.vhdl file: <nowiki>library IEEE;
		+	use IEEE.STD_LOGIC_1164.ALL;
		+	use IEEE.NUMERIC_STD.ALL;
		+
		+	entity commands is
		+	port (
		+	count:in unsigned (63 downto 0);
		+	data1: inout unsigned (63 downto 0)
		+	);
		+	end commands;
		+
		+	architecture Behavioral of commands is
		+
		+	begin
		+	data1<=count +1;
		+	end Behavioral;</nowiki>

← Older revision		Revision as of 15:06, 31 January 2014
Line 95:		Line 95:
	</nowiki>		</nowiki>
	So, now everything is working again.		So, now everything is working again.
		+
		+	=Entity port data5 does not match with type unsigned of component port=
		+	They do match, but somehow Xilinx 14.5 doesn't like it. Looks like issue [http://www.xilinx.com/support/answers/33877.htm 33877], but that was for 11.4 (and the proposed solution doesn't work, I did try).

@@ Line 54: / Line 54: @@
 =Cannot compile generated C files=
-Don't know the solution to this one yet, when trying to simulate (maybe it started happening after I upgraded to Ubuntu 13.04)
+When trying to simulate, the simulator responds with errors; the fix was to use gcc-4.4 (maybe the problem started after I upgraded to Ubuntu 13.04, it also persists in 13.10)
  <nowiki>Waiting for 2 sub-compilation(s) to finish...
 FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the generated C files.

@@ Line 8: / Line 8: @@
 =ISE WebPACK for Linux notes=
 * Free edition of software: [http://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.htm ISE WebPACK]
  $ md5sum ~/Downloads/Xilinx_ISE_DS_Lin_14.5_P.58f_4.tar

@@ Line 37: / Line 37: @@
  cd /usr/lib/chromium-browser
  mv chromium-browser chromium_browser_
- cat > crhomium-browser <<EOF
+ cat > chromium-browser <<EOF
  #!/bin/bash
  LD_LIBRARY_PATH=