Revision history of "File:Bscan s3 spi isf-reset.vhdl"

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  • curprev 23:03, 6 June 2013‎ Joosteto talk contribs‎ 203 bytes +203‎ bscan.vhdl to program Flash via xc3s500E (and others?) FPGA's. Changes: * resets 'header' signal after setting have_header<='0' * changes to make my Xilinx ISE 14.5 accept it (mostly remove SPI_ACCESS)
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