FPGA Clock/Trigger generator

First, for the differential signals, (information copied from Hamster Code]

NET test_sig_out_n LOC = "P12"; # C12
NET test_sig_out_p LOC = "P11"; # C11

NET test_sig_in_p LOC = "P15"; # C13
NET test_sig_in_n LOC = "P16"; # C14

Then, do drive the signals, use in VHDL:

output_buffer: OBUFDS 
   generic map ( IOSTANDARD => "LVDS_25") 
   port map (
      O => test_sig_out_p, 
      OB => test_sig_out_n,
      I => test_sig_out    
   );
input_buffer : IBUFDS 
   generic map (
      DIFF_TERM => TRUE,
      IBUF_DELAY_VALUE => "0", 
      IFD_DELAY_VALUE => "AUTO",
      IOSTANDARD => "LVDS_25")
   port map (
      O  => test_sig_in,   -- Buffer output
      I  => test_sig_in_p, -- Diff_p buffer input (connect directly to top-level port)
      IB => test_sig_in_n  -- Diff_n buffer input (connect directly to top-level port)
   );