Difference between revisions of "FPGA Clock/Trigger generator"
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==Xilinx code to drive Differential signals== |
==Xilinx code to drive Differential signals== |
||
| − | information copied from [http://hamsterworks.co.nz/mediawiki/index.php/High_Speed_Link Hamster Code |
+ | information copied from [http://hamsterworks.co.nz/mediawiki/index.php/High_Speed_Link Hamster Code] |
<nowiki>NET test_sig_out_n LOC = "P12"; # C12 |
<nowiki>NET test_sig_out_n LOC = "P12"; # C12 |
||
Revision as of 13:32, 21 May 2013
- DLL1: CLKIN=32MHz -> *25, /4 -> 100MHz
- DLL2: CLKIN=100Mhz -> *5, /7 -> 71.428MHz
- DLL3: CLKIN=71.428MHz/2
- DLL4: CLKIN=142.86MHz
MR <=MR1 xor MR2
MR1<=CLKIN3
MR2<=CLKIN3, variable phase delayed
CCR <=
if rising_edge(CLKIN4) then
CCR<=trigger xor CCRCLK;
CCRCLK<=not CCRCLK;
fi
differential signals
Measurements
When defining an output as LVDS_25:
- Voltage over + and - pair: 0.559 / -0.558 V
- Current (when shorted): 10.69/10.62 mA
- Voltage over GND and + (or -): 1.53 / 0.97V
Available Lines
- C2/C3 = P94/P95 = IO_L06
- C5/C6 = P2/P3 = IO_L01
- C7/C8 = P4/P5 = IO_L02
- C9/C10 = P9/P10 = IO_L03
Xilinx code to drive Differential signals
information copied from Hamster Code
NET test_sig_out_n LOC = "P12"; # C12 NET test_sig_out_p LOC = "P11"; # C11 NET test_sig_in_p LOC = "P15"; # C13 NET test_sig_in_n LOC = "P16"; # C14
Then, to drive/read the differential signals, use in VHDL:
library UNISIM;
use UNISIM.VComponents.all;
--
--
output_buffer: OBUFDS
generic map ( IOSTANDARD => "LVDS_25")
port map (
O => test_sig_out_p,
OB => test_sig_out_n,
I => test_sig_out
);
input_buffer : IBUFDS
generic map (
DIFF_TERM => TRUE,
IBUF_DELAY_VALUE => "0",
IFD_DELAY_VALUE => "AUTO",
IOSTANDARD => "LVDS_25")
port map (
O => test_sig_in, -- Buffer output
I => test_sig_in_p, -- Diff_p buffer input (connect directly to top-level port)
IB => test_sig_in_n -- Diff_n buffer input (connect directly to top-level port)
);
