Difference between revisions of "FPGA Test Board"

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=TODO=
 
=TODO=
 
==layout==
 
==layout==
* Add SUSSync check lines (+ resistor, + protection(?))
 
 
* Add header for TTL out lines (with connections to Spartan 6 & 3)
 
* Add header for TTL out lines (with connections to Spartan 6 & 3)
 
* add location for oven-controlled crystal
 
* add location for oven-controlled crystal

Revision as of 02:49, 17 December 2013

TODO

layout

  • Add header for TTL out lines (with connections to Spartan 6 & 3)
  • add location for oven-controlled crystal
  • Check layout 25MHz crystal (same as 32MHz papilio?)
  • Power connector?

questions

  • what are the Check lines (Config 1&2 on pins 13 and 14; are they reversed on sender/receiver (source/sink)?) (wiki )

Components



Xilinx PCB design guides

Other stuff

Todo/tocheck

  • make papilio output +/- 71MHz differential signal, at several differential voltages.
  • add footprints to eagle
  • can spartan-differential easily be made compatible with rs484?

See Also