Difference between revisions of "Xilinx"

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* Xilinx constrants.ucf file info [http://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf Constraints Guide]
  
* Xilinx constrants.ucf file info [http://www.xilinx.com/itp/xilinx10/books/docs/cgd/cgd.pdf Constraints Guide]
 
* programming (sending .bit file to FPGA) via [http://xc3sprog.sourceforge.net/hardware.php xc3sprog]?
  
* programming (sending .bit file to FPGA) via [http://xc3sprog.sourceforge.net/hardware.php xc3sprog]?
  +
  +
=Directly programming Spartan via JTAG=
  +
[[Directly programming Spartan via JTAG]]
   
 
=ISE WebPACK for Linux notes=
  
=ISE WebPACK for Linux notes=
Line 23: Line 26:
 
#Set the env variables:
  
#Set the env variables:
 
INSTALL_DIR=/opt
  
INSTALL_DIR=/opt
  +
VER=14.5
−
 
−
. $INSTALL_DIR/Xilinx/14.5/ISE_DS/settings32.sh
 +
. $INSTALL_DIR/Xilinx/$VER/ISE_DS/settings32.sh
⚫
#bugfix for 14.4:
  
⚫
#export XIL_CG_LOAD_ALL_FAMILIES=true
  
⚫
#DISPLAY=:0
  
 
 
 
#starting the main app:
  
#starting the main app:
−
$INSTALL_DIR/Xilinx/14.5/ISE_DS/ISE/bin/lin/ise
 +
$INSTALL_DIR/Xilinx/$VER/ISE_DS/ISE/bin/lin/ise
 
 
 
#starting coregen:
  
#starting coregen:
−
$INSTALL_DIR/Xilinx/14.5/ISE_DS/ISE/bin/lin/coregen
 +
$INSTALL_DIR/Xilinx/$VER/ISE_DS/ISE/bin/lin/coregen
  +
  ⚫
#bugfix for 14.4, before startning ise etc:
  ⚫
#export XIL_CG_LOAD_ALL_FAMILIES=true
  ⚫
#DISPLAY=:0
  +
 
==Issues (14.4)==
  
==Issues (14.4)==
 
* When first starting <tt>ise</tt>, it will ask for a license by starting a browser (chromium on my system). But as it sets the LD_LIBRARY_PATH variable to Xilinx-compiles stdc++ library, chromium-browser cannot start start. As the licence manager doesn't inform the user of the crashed browser, simply nothing happens after clikcing the 'get licence' (or whatever it was called) button. I fixed this with:
  
* When first starting <tt>ise</tt>, it will ask for a license by starting a browser (chromium on my system). But as it sets the LD_LIBRARY_PATH variable to Xilinx-compiles stdc++ library, chromium-browser cannot start start. As the licence manager doesn't inform the user of the crashed browser, simply nothing happens after clikcing the 'get licence' (or whatever it was called) button. I fixed this with:
Line 98: Line 103:
 
=Entity port data5 does not match with type unsigned of component port=
  
=Entity port data5 does not match with type unsigned of component port=
 
They do match, but somehow Xilinx 14.5 doesn't like it. Looks like issue [http://www.xilinx.com/support/answers/33877.htm 33877], but that was for 11.4 (and the proposed solution doesn't work, I did try).
  
They do match, but somehow Xilinx 14.5 doesn't like it. Looks like issue [http://www.xilinx.com/support/answers/33877.htm 33877], but that was for 11.4 (and the proposed solution doesn't work, I did try).
  +
  +
Solution: replace the [http://forums.xilinx.com/t5/Synthesis/Entity-port-count-does-not-match-with-type-unsigned-of-component/m-p/409407#M10070 use IEEE.NUMERIC_STD.ALL;] with use IEEE.NUMERIC_STD.ALL in the commands.vhdl file.
  +
  +
The complaint happens in the "Synthesize XST" phase ("View RTL Schematic").
  +
  +
With the following main.vhdl file
  +
<nowiki>library IEEE;
  +
use IEEE.STD_LOGIC_1164.ALL;
  +
use IEEE.NUMERIC_STD.ALL;
  +
  +
entity commands is
  +
port (
  +
count:in unsigned (63 downto 0);
  +
data1: inout unsigned (63 downto 0)
  +
);
  +
end commands;
  +
  +
architecture Behavioral of commands is
  +
  +
begin
  +
data1<=count +1;
  +
end Behavioral;</nowiki>
  +
  +
And the following commands.vhdl file:
  +
<nowiki>library IEEE;
  +
use IEEE.STD_LOGIC_1164.ALL;
  +
use IEEE.NUMERIC_STD.ALL;
  +
  +
entity commands is
  +
port (
  +
count:in unsigned (63 downto 0);
  +
data1: inout unsigned (63 downto 0)
  +
);
  +
end commands;
  +
  +
architecture Behavioral of commands is
  +
  +
begin
  +
data1<=count +1;
  +
end Behavioral;</nowiki>

Latest revision as of 18:37, 16 July 2015

Notes about Xilinx

Directly programming Spartan via JTAG

Directly programming Spartan via JTAG

ISE WebPACK for Linux notes

  • Generate self-checking testbench: [1]
  • Free edition of software: ISE WebPACK
$ md5sum ~/Downloads/Xilinx_ISE_DS_Lin_14.5_P.58f_4.tar 
328ebf4cdd0f08ee56e116dd88d6cc4c  /home/joostje/Downloads/Xilinx_ISE_DS_Lin_14.5_P.58f_4.tar
#
tar -xvf Xilinx_ISE_DS_Lin_14.5_P.58f_4.tar
cd Xilinx_ISE_DS_Lin_14.5_P.58f_4
./xsetup
#After the licences, Select ISE-WebPack

#Installing libXm.so.3:
sudo apt-get install libmotif3

#Set the env variables:
INSTALL_DIR=/opt
VER=14.5
. $INSTALL_DIR/Xilinx/$VER/ISE_DS/settings32.sh

#starting the main app:
$INSTALL_DIR/Xilinx/$VER/ISE_DS/ISE/bin/lin/ise

#starting coregen:
$INSTALL_DIR/Xilinx/$VER/ISE_DS/ISE/bin/lin/coregen

#bugfix for 14.4, before startning ise etc:
#export XIL_CG_LOAD_ALL_FAMILIES=true
#DISPLAY=:0

Issues (14.4)

  • When first starting ise, it will ask for a license by starting a browser (chromium on my system). But as it sets the LD_LIBRARY_PATH variable to Xilinx-compiles stdc++ library, chromium-browser cannot start start. As the licence manager doesn't inform the user of the crashed browser, simply nothing happens after clikcing the 'get licence' (or whatever it was called) button. I fixed this with:
cd /usr/lib/chromium-browser
mv chromium-browser chromium_browser_
cat > chromium-browser <<EOF
#!/bin/bash
LD_LIBRARY_PATH=
set > /tmp/set
/usr/lib/chromium-browser/chromium-browser_ "$@"
EOF
chmod a+x chromium-browser

This will of cause stop working after the next update of chromium-browser.

  • Coregen doesn't load the full IP library (or something). Fixed this with the XIL_CG_LOAD_ALL_FAMILIES=true environment variable above. If you don't do this, the IP Core generator gives these messages in the console:
ERROR:encore:372 - Failed to set default project options.
ERROR:sim:569 - Failed to set default project options.
ERROR:encore:268 - Project /home/joostje/VHDL/Ltest/coregen_xil_1hPILG.cgc could not be opened
ERROR:encore:312 - Couldn't create new project.

Cannot compile generated C files

When trying to simulate, the simulator responds with errors; the fix was to use gcc-4.4 (maybe the problem started after I upgraded to Ubuntu 13.04, it also persists in 13.10) 

Waiting for 2 sub-compilation(s) to finish...
FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the generated C files.

   Please recompile with -mt off -v 1 switch to identify which design unit failed.  Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the generated C files.

   Please recompile with -mt off -v 1 switch to identify which design unit failed.  Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Process "Simulate Behavioral Model" failed

When running the last mentioned with added -mt off -v 1, I get these messages: 

cd <toplevel-project-dir>
/home/joostje/Xilinx/14.5/ISE_DS/ISE/bin/lin/unwrapped/fuse -intstyle ise -incremental -o /home/joostje/VHDL/TM1638_2/tm1638/tb_isim_beh.exe -mt off -v 1 -prj /home/joostje/VHDL/TM1638_2/tm1638/tb_beh.prj work.tb

Compiling isim/tb_isim_beh.exe.sim/work/tb_isim_beh.exe_main.c to isim/tb_isim_beh.exe.sim/work/tb_isim_beh.exe_main.lin.o with command:
"/usr/bin/gcc" -Wa,-W  -O  -m32  -c -o "isim/tb_isim_beh.exe.sim/work/tb_isim_beh.exe_main.lin.o" -I"/home/joostje/Xilinx/14.5/ISE_DS/ISE/data/include" "isim/tb_isim_beh.exe.sim/work/tb_isim_beh.exe_main.c"
/usr/lib/gcc/i686-linux-gnu/4.7/cc1: /home/joostje/Xilinx/14.5/ISE_DS/ISE/lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/i386-linux-gnu/libppl_c.so.4)
/usr/lib/gcc/i686-linux-gnu/4.7/cc1: /home/joostje/Xilinx/14.5/ISE_DS/ISE/lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/i386-linux-gnu/libppl_c.so.4)
/usr/lib/gcc/i686-linux-gnu/4.7/cc1: /home/joostje/Xilinx/14.5/ISE_DS/ISE/lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.15' not found (required by /usr/lib/i386-linux-gnu/libppl_c.so.4)
/usr/lib/gcc/i686-linux-gnu/4.7/cc1: /home/joostje/Xilinx/14.5/ISE_DS/ISE/lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.11' not found (required by /usr/lib/i386-linux-gnu/libppl.so.12)
/usr/lib/gcc/i686-linux-gnu/4.7/cc1: /home/joostje/Xilinx/14.5/ISE_DS/ISE/lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.9' not found (required by /usr/lib/i386-linux-gnu/libppl.so.12)
/usr/lib/gcc/i686-linux-gnu/4.7/cc1: /home/joostje/Xilinx/14.5/ISE_DS/ISE/lib/lin/libstdc++.so.6: version `GLIBCXX_3.4.15' not found (required by /usr/lib/i386-linux-gnu/libppl.so.12)
FATAL_ERROR:Simulator:Fuse.cpp:500:1.133 - Failed to compile generated C file isim/tb_isim_beh.exe.sim/work/tb_isim_beh.exe_main.c

Installing gcc-4.4, and symlinking gcc to gcc-4.4, 

aptitude install gcc-4.4
cd /usr/bin/
ln -sf gcc-4.4 gcc

fixed it the compilation error. I did have to remove the isim dir in the top level project dir, to remove the linking errors: 

gcc-4.4.real: isim/precompiled.exe.sim/ieee/p_2592010699.lin.o: No such file or directory
gcc-4.4.real: isim/precompiled.exe.sim/ieee/p_1242562249.lin.o: No such file or directory
gcc-4.4.real: isim/tb_isim_beh.exe.sim/work/p_1475539293.lin.o: No such file or directory
gcc-4.4.real: isim/tb_isim_beh.exe.sim/work/a_2254175691_3212880686.lin.o: No such file or directory
gcc-4.4.real: isim/tb_isim_beh.exe.sim/work/a_0006416349_3212880686.lin.o: No such file or directory
gcc-4.4.real: isim/tb_isim_beh.exe.sim/work/a_0712399306_3212880686.lin.o: No such file or directory
gcc-4.4.real: isim/tb_isim_beh.exe.sim/work/a_3185013696_3212880686.lin.o: No such file or directory
gcc-4.4.real: isim/tb_isim_beh.exe.sim/work/a_3671711236_2372691052.lin.o: No such file or directory

So, now everything is working again.

Entity port data5 does not match with type unsigned of component port

They do match, but somehow Xilinx 14.5 doesn't like it. Looks like issue 33877, but that was for 11.4 (and the proposed solution doesn't work, I did try).

Solution: replace the use IEEE.NUMERIC_STD.ALL; with use IEEE.NUMERIC_STD.ALL in the commands.vhdl file.

The complaint happens in the "Synthesize XST" phase ("View RTL Schematic").

With the following main.vhdl file 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity commands is
  port (
    count:in unsigned (63 downto 0);
    data1: inout unsigned (63 downto 0)
    );
end commands;

architecture Behavioral of commands is

begin
  data1<=count +1;
end Behavioral;

And the following commands.vhdl file: 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity commands is
  port (
    count:in unsigned (63 downto 0);
    data1: inout unsigned (63 downto 0)
    );
end commands;

architecture Behavioral of commands is

begin
  data1<=count +1;
end Behavioral;
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