Difference between revisions of "FPGA Test Board"

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==questions==
 
==questions==
* polarity of CCR on Display Port cable? ([http://en.wikipedia.org/wiki/Display_port wiki] has pin 7 as +lane_2, wim pin 7 as -CCR) -- Oh, that's because the sink-side has the pinning reversed -- but then the polarity of MR is wrong
+
* what are the Check lines (Config 1&2 on pins 13 and 14?) ([http://en.wikipedia.org/wiki/Display_port wiki] )
   
 
=Components=
 
=Components=

Revision as of 23:07, 15 December 2013

TODO

layout

  • Add SUSSync check lines (+ resistor, + protection(?))
  • Add few LEDs to spartan 3
  • add location for oven-controlled crystal
  • Check layout 25MHz crystal (same as 32MHz papilio?)
  • Power connector?

questions

  • what are the Check lines (Config 1&2 on pins 13 and 14?) (wiki )

Components



Xilinx PCB design guides

Other stuff

Todo/tocheck

  • make papilio output +/- 71MHz differential signal, at several differential voltages.
  • add footprints to eagle
  • can spartan-differential easily be made compatible with rs484?

See Also