Xilinx

Notes about Xilinx

• Website: http://www.xilinx.com/products/silicon-devices/fpga/
• Spartan 3a Starter Board: SPARTAN-3E, BASYS2, FPGA, EVAL BOARD (Board Guide) Spartan 3a user guide, Data Sheet
• examples
• Butterfly One: board with schematics. Docs at papilio (with eagle files), SparkFun page, forum, XC3S500E datasheet
• Xilinx constrants.ucf file info Constraints Guide
• programming (sending .bit file to FPGA) via xc3sprog?

ISE WebPACK for Linux notes

• Free edition of software: ISE WebPACK

$ md5sum ~/Downloads/Xilinx_ISE_DS_Lin_14.5_P.58f_4.tar 
328ebf4cdd0f08ee56e116dd88d6cc4c  /home/joostje/Downloads/Xilinx_ISE_DS_Lin_14.5_P.58f_4.tar
#
tar -xvf Xilinx_ISE_DS_Lin_14.5_P.58f_4.tar
cd Xilinx_ISE_DS_Lin_14.5_P.58f_4
./xsetup
#After the licences, Select ISE-WebPack

#Installing libXm.so.3:
sudo apt-get install libmotif3

#Set the env variables:
INSTALL_DIR=/opt

. $INSTALL_DIR/Xilinx/14.5/ISE_DS/settings32.sh
#bugfix for 14.4:
#export XIL_CG_LOAD_ALL_FAMILIES=true
#DISPLAY=:0

#starting the main app:
$INSTALL_DIR/Xilinx/14.5/ISE_DS/ISE/bin/lin/ise

#starting coregen:
$INSTALL_DIR/Xilinx/14.5/ISE_DS/ISE/bin/lin/coregen

Issues (14.4)

• When first starting ise, it will ask for a license by starting a browser (chromium on my system). But as it sets the LD_LIBRARY_PATH variable to Xilinx-compiles stdc++ library, chromium-browser cannot start start. I fixed this with:

cd /usr/lib/chromium-browser
mv chromium-browser chromium_browser_
cat > crhomium-browser <<EOF
#!/bin/bash
LD_LIBRARY_PATH=
set > /tmp/set
/usr/lib/chromium-browser/chromium-browser_ "$@"
EOF
chmod a+x chromium-browser.

This will of cause stop working after the next update of chromium-browser.

• Coregen doesn't load the full IP library (or something). Fixed this with the XIL_CG_LOAD_ALL_FAMILIES=true environment variable above. If you don't do this, the IP Core generator gives these messages in the console:

ERROR:encore:372 - Failed to set default project options.
ERROR:sim:569 - Failed to set default project options.
ERROR:encore:268 - Project /home/joostje/VHDL/Ltest/coregen_xil_1hPILG.cgc could not be opened
ERROR:encore:312 - Couldn't create new project.

• Simulation fail:

Don't know the solution to this one yet, when trying to simulate (maybe it started happening after I upgraded to Ubuntu 13.04)

Waiting for 2 sub-compilation(s) to finish...
FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the generated C files.

   Please recompile with -mt off -v 1 switch to identify which design unit failed.  Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
FATAL_ERROR:Simulator:Fuse.cpp:209:1.133 - Failed to compile one of the generated C files.

   Please recompile with -mt off -v 1 switch to identify which design unit failed.  Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.

Process "Simulate Behavioral Model" failed