DCM module VHDL code
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Jump to navigationJump to searchWith the following 3 files (the DCM part is generated by the IPCoreGen of Xilinx), the DCM module can be made to work without the having to run the IP CORE generator.
Similar code can also be found in: Edit/Language Templates..., and then select Spartan 3, Clock Components, Clock MUX.
Top level LEDtest.vhdl:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity LEDtest is
port (
clk_in: in std_logic;
LED1: out std_logic;
LED2: out std_logic
);
end LEDtest;
architecture BEHAVIOUR of LEDtest is
component DCM71 port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end component;
signal count: integer range 0 to 114285719 := 0;
signal clk: std_logic;
signal clk0: std_logic;
signal sec:integer range 0 to 3600 :=0;
signal duration: integer range 0 to 32000000 := 1000000;
signal tmp: std_logic_vector(0 downto 0);
begin
Inst_DCM71: DCM71 port map(
CLKIN_IN =>clk_in,
CLKFX_OUT =>clk,
CLKIN_IBUFG_OUT =>open,
CLK0_OUT =>clk0,
LOCKED_OUT =>open);
IN_process: process (clk)
begin
if clk'event and clk = '1' then
count<=count+1;
if count<duration then
LED1<='1';
else
LED1<='0';
end if;
LED2<=tmp(0);
if count>=114285714 then
count<=0;
sec<=sec+1;
tmp <=conv_std_logic_vector(sec, 1);
if sec=9 then
sec<=0;
duration<=32000000;
else
duration<=1000000;
end if;
end if;
end if;
end process;
end BEHAVIOUR;
The DCM71.vhdl file (I call it '71' as it's supposed to convert a 20MHz clock into 71.428...MHz):
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 12.4
-- \ \ Application : xaw2vhdl
-- / / Filename : DCM71.vhd
-- /___/ /\ Timestamp : 04/18/2013 14:47:31
-- \ \ / \
-- \___\/\___\
--
--Design Name: DCM71
--Device: xc3s500e-4vq100
--
-- Module DCM71
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;
entity DCM71 is
port ( CLKIN_IN : in std_logic;
CLKFX_OUT : out std_logic;
CLKIN_IBUFG_OUT : out std_logic;
CLK0_OUT : out std_logic;
LOCKED_OUT : out std_logic);
end DCM71;
architecture BEHAVIORAL of DCM71 is
signal CLKFB_IN : std_logic;
signal CLKFX_BUF : std_logic;
signal CLKIN_IBUFG : std_logic;
signal CLK0_BUF : std_logic;
signal GND_BIT : std_logic;
begin
GND_BIT <= '0';
CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
CLK0_OUT <= CLKFB_IN;
CLKFX_BUFG_INST : BUFG
port map (I=>CLKFX_BUF,
O=>CLKFX_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (I=>CLKIN_IN,
O=>CLKIN_IBUFG);
CLK0_BUFG_INST : BUFG
port map (I=>CLK0_BUF,
O=>CLKFB_IN);
DCM_SP_INST : DCM_SP
generic map( CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 7,
CLKFX_MULTIPLY => 25,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 50.000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"C080",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (CLKFB=>CLKFB_IN,
CLKIN=>CLKIN_IBUFG,
DSSEN=>GND_BIT,
PSCLK=>GND_BIT,
PSEN=>GND_BIT,
PSINCDEC=>GND_BIT,
--RST=>RST_IN,
RST=>GND_BIT,
CLKDV=>open,
CLKFX=>CLKFX_BUF,
CLKFX180=>open,
CLK0=>CLK0_BUF,
CLK2X=>open,
CLK2X180=>open,
CLK90=>open,
CLK180=>open,
CLK270=>open,
LOCKED=>LOCKED_OUT,
PSDONE=>open,
STATUS=>open);
end BEHAVIORAL;
And the constraints.ucf file:
# Crystal Clock - use 32MHz onboard oscillator NET "clk_in" LOC = "P89" | IOSTANDARD = LVCMOS25 | PERIOD = 50.0ns ; # Wing1 Column A NET "LED1" LOC = "P91"; NET "LED2" LOC = "P92";
If you encounter errors like these:
ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:NgdBuild:981 - Could not find any associations for the following constraint: ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLK_FEEDBACK = 1X;> [constraints.ucf(12)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKDV_DIVIDE = 2.0;> [constraints.ucf(13)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKFX_DIVIDE = 7;> [constraints.ucf(14)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKFX_MULTIPLY = 25;> [constraints.ucf(15)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE;> [constraints.ucf(16)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKIN_PERIOD = 50.000;> [constraints.ucf(17)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE;> [constraints.ucf(18)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;> [constraints.ucf(19)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW;> [constraints.ucf(20)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW;> [constraints.ucf(21)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE;> [constraints.ucf(22)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST FACTORY_JF = C080;> [constraints.ucf(23)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST PHASE_SHIFT = 0;> [constraints.ucf(24)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file. ERROR:ConstraintSystem:59 - Constraint <INST DCM_SP_INST STARTUP_WAIT = FALSE;> [constraints.ucf(25)]: INST "DCM_SP_INST" not found. Please verify that: 1. The specified design element actually exists in the original design. 2. The specified object is spelled correctly in the constraint source file.
Then the solution is simple: DO NOT INCLUDE the DCM_arwz.ucf file generated by IP CoreGenerator!
So, IGNORE the following file in ipcore_dir:
# Generated by Xilinx Architecture Wizard # --- UCF Template Only --- # Cut and paste these attributes into the project's UCF file, if desired INST DCM_SP_INST CLK_FEEDBACK = 1X; INST DCM_SP_INST CLKDV_DIVIDE = 2.0; INST DCM_SP_INST CLKFX_DIVIDE = 7; INST DCM_SP_INST CLKFX_MULTIPLY = 25; INST DCM_SP_INST CLKIN_DIVIDE_BY_2 = FALSE; INST DCM_SP_INST CLKIN_PERIOD = 50.000; INST DCM_SP_INST CLKOUT_PHASE_SHIFT = NONE; INST DCM_SP_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS; INST DCM_SP_INST DFS_FREQUENCY_MODE = LOW; INST DCM_SP_INST DLL_FREQUENCY_MODE = LOW; INST DCM_SP_INST DUTY_CYCLE_CORRECTION = TRUE; INST DCM_SP_INST FACTORY_JF = C080; INST DCM_SP_INST PHASE_SHIFT = 0; INST DCM_SP_INST STARTUP_WAIT = FALSE;
