Difference between revisions of "FPGA Clock/Trigger generator"

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(Created page with "First, for the differential signals, (information copied from [http://hamsterworks.co.nz/mediawiki/index.php/High_Speed_Link Hamster Code]] <nowiki>NET test_sig_out_n LOC = "P1…")
 
 
(15 intermediate revisions by the same user not shown)
Line 1: Line 1:
  +
* DLL1: CLKIN=32MHz -> *25, /8 -> 100MHz
⚫
First, for the differential signals, (information copied from [http://hamsterworks.co.nz/mediawiki/index.php/High_Speed_Link Hamster Code]]
  
  +
* DLL2: CLKIN=100Mhz -> *5, /7 -> 71.428MHz
  +
* DLL3: CLKIN=71.428MHz/2
  +
* DLL4: CLKIN=142.86MHz
  +
converting frequencies using [[DCM module VHDL code]]
  +
<nowiki>
  +
MR <=MR1 xor MR2
  +
MR1<=CLKIN3
  +
MR2<=CLKIN3, variable phase delayed
  +
  +
CCR <=
  +
if rising_edge(CLKIN4) then
  +
CCR<=trigger xor CCRCLK;
  +
CCRCLK<=not CCRCLK;
  +
fi
  +
</nowiki>
  +
=differential signals=
  +
==Measurements==
  +
When defining an output as LVDS_25 (VCCO jumper to 3.3V):
  +
* Voltage over + and - pair: 0.559 / -0.558 V
  +
* Current (when shorted): 10.69/-10.62 mA
  +
* Voltage over GND and + (or -): 1.53 / 0.97V
  +
  +
VCCO Jumper to 2.5V:
  +
* Voltage over + and - pair: 0.567 / -0.565 V
  +
* Current (when shorted): 10.71 / -10.64 mA
  +
* Voltage over GND and + (or -): 1.53 / 0.97V
  +
  +
VCCO Jumper to 1.2V:
  +
* Voltage over + and - pair: ? / -0.5228 V
  +
* Current (when shorted): ? / 4.59 mA
  +
* Voltage over GND and + / - : 0.27 / 0.79 V
  +
  +
==Available Lines==
  +
As I'm using (4 pins on) the right-side for the DX Display TM1638 connection, I try to only use the left side; some of the available differential pins are:
  +
*C2/C3 = P94/P95 = IO_L06 (P94 connected to single-signal)
  +
*C5/C6 = P2/P3 = IO_L01
  +
*C7/C8 = P4/P5 = IO_L02
  +
*C9/C10 = P9/P10 = IO_L03 (P9/P10 connected to differential)
  +
  +
==Xilinx code to drive Differential signals==
  ⚫
information copied from [http://hamsterworks.co.nz/mediawiki/index.php/High_Speed_Link Hamster Code]
   
 
<nowiki>NET test_sig_out_n LOC = "P12"; # C12
  
<nowiki>NET test_sig_out_n LOC = "P12"; # C12
Line 7: Line 48:
 
NET test_sig_in_n LOC = "P16"; # C14</nowiki>
  
NET test_sig_in_n LOC = "P16"; # C14</nowiki>
   
−
Then, do drive the signals, use in VHDL:
 +
Then, to drive/read the differential signals, use in VHDL:
  +
<nowiki>
⚫
<nowiki>output_buffer: OBUFDS generic map ( IOSTANDARD => "LVDS_25") port map (
  
  +
  +
  +
library UNISIM;
  +
use UNISIM.VComponents.all;
  +
--
  +
--
  +
output_buffer: OBUFDS
  ⚫
generic map ( IOSTANDARD => "LVDS_25")
  +
port map (
 
O => test_sig_out_p,
 
O => test_sig_out_p,
 
OB => test_sig_out_n,
  
OB => test_sig_out_n,
 
I => test_sig_out
 
I => test_sig_out
 
);
  
);
−
input_buffer : IBUFDS generic map (
 +
input_buffer : IBUFDS
  +
generic map (
 
DIFF_TERM => TRUE,
  
DIFF_TERM => TRUE,
 
IBUF_DELAY_VALUE => "0",
 
IBUF_DELAY_VALUE => "0",

Latest revision as of 00:27, 28 May 2013

  • DLL1: CLKIN=32MHz -> *25, /8 -> 100MHz
  • DLL2: CLKIN=100Mhz -> *5, /7 -> 71.428MHz
  • DLL3: CLKIN=71.428MHz/2
  • DLL4: CLKIN=142.86MHz

converting frequencies using DCM module VHDL code 

MR <=MR1 xor MR2
MR1<=CLKIN3
MR2<=CLKIN3, variable phase delayed

CCR <= 
  if rising_edge(CLKIN4) then
    CCR<=trigger xor CCRCLK;
    CCRCLK<=not CCRCLK;
  fi

differential signals

Measurements

When defining an output as LVDS_25 (VCCO jumper to 3.3V):

  • Voltage over + and - pair: 0.559 / -0.558 V
  • Current (when shorted): 10.69/-10.62 mA
  • Voltage over GND and + (or -): 1.53 / 0.97V

VCCO Jumper to 2.5V:

  • Voltage over + and - pair: 0.567 / -0.565 V
  • Current (when shorted): 10.71 / -10.64 mA
  • Voltage over GND and + (or -): 1.53 / 0.97V

VCCO Jumper to 1.2V:

  • Voltage over + and - pair: ? / -0.5228 V
  • Current (when shorted): ? / 4.59 mA
  • Voltage over GND and + / - : 0.27 / 0.79 V

Available Lines

As I'm using (4 pins on) the right-side for the DX Display TM1638 connection, I try to only use the left side; some of the available differential pins are:

  • C2/C3 = P94/P95 = IO_L06 (P94 connected to single-signal)
  • C5/C6 = P2/P3 = IO_L01
  • C7/C8 = P4/P5 = IO_L02
  • C9/C10 = P9/P10 = IO_L03 (P9/P10 connected to differential)

Xilinx code to drive Differential signals

information copied from Hamster Code 

NET test_sig_out_n LOC = "P12"; # C12
NET test_sig_out_p LOC = "P11"; # C11

NET test_sig_in_p LOC = "P15"; # C13
NET test_sig_in_n LOC = "P16"; # C14

Then, to drive/read the differential signals, use in VHDL: 



library UNISIM;
use UNISIM.VComponents.all;
--
--
output_buffer: OBUFDS 
   generic map ( IOSTANDARD => "LVDS_25") 
   port map (
      O => test_sig_out_p, 
      OB => test_sig_out_n,
      I => test_sig_out    
   );
input_buffer : IBUFDS 
   generic map (
      DIFF_TERM => TRUE,
      IBUF_DELAY_VALUE => "0", 
      IFD_DELAY_VALUE => "AUTO",
      IOSTANDARD => "LVDS_25")
   port map (
      O  => test_sig_in,   -- Buffer output
      I  => test_sig_in_p, -- Diff_p buffer input (connect directly to top-level port)
      IB => test_sig_in_n  -- Diff_n buffer input (connect directly to top-level port)
   );
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