DCM module VHDL code

With the following 3 files, the DCM module can be made to work without the IP CORE generator.

Top level LEDtest.vhdl:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LEDtest is
  port (
    clk_in: in std_logic;
	 LED1: out std_logic;
	 LED2: out std_logic
  );
end LEDtest;


architecture BEHAVIOUR of LEDtest is
    component DCM71  port ( CLKIN_IN        : in    std_logic; 
          CLKFX_OUT       : out   std_logic; 
          CLKIN_IBUFG_OUT : out   std_logic; 
          CLK0_OUT        : out   std_logic; 
          LOCKED_OUT      : out   std_logic);
    end component;

    signal count: integer range 0 to 32000000 := 0;
	 signal clk: std_logic;
	 signal clk0: std_logic;
	 signal sec:integer range 0 to 3600 :=0;
	 signal duration: integer range 0 to 32000000 := 1000000;
	 signal tmp: std_logic_vector(0 downto 0);
	 
begin
  Inst_DCM71: DCM71 port map(
          CLKIN_IN        =>clk_in, 
          CLKFX_OUT       =>clk,
          CLKIN_IBUFG_OUT =>open, 
          CLK0_OUT        =>clk0, 
          LOCKED_OUT      =>open);
  IN_process: process (clk)
    begin
      if clk'event and clk = '1' then
		  count<=count+1;
		  if count<duration then
		    LED1<='1';
		  else
		    LED1<='0';
		  end if;
		  LED2<=tmp(0);
		  if count=31999999 then
		    count<=0;
			 sec<=sec+1;
			 tmp <=conv_std_logic_vector(sec, 1);
			 if sec=9 then
			   sec<=0;
				duration<=16000000;
			 else
			   duration<=10000000;
			 end if;
		  end if;  
		end if;
    end process;
end BEHAVIOUR;

The DCM71.vhdl file (I call it '71' as it's supposed to convert a 25MHz clock into 71.428...MHz):

--------------------------------------------------------------------------------
-- Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 12.4
--  \   \         Application : xaw2vhdl
--  /   /         Filename : DCM71.vhd
-- /___/   /\     Timestamp : 04/18/2013 14:47:31
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: xaw2vhdl-st C:\\Xilinx\12.4\ISE_DS\ISE\.\DCM71.xaw C:\\Xilinx\12.4\ISE_DS\ISE\.\DCM71
--Design Name: DCM71
--Device: xc3s500e-4vq100
--
-- Module DCM71
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST
-- Period Jitter (unit interval) for block DCM_SP_INST = 0.08 UI
-- Period Jitter (Peak-to-Peak) for block DCM_SP_INST = 1.06 ns

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity DCM71 is
   port ( CLKIN_IN        : in    std_logic; 
          CLKFX_OUT       : out   std_logic; 
          CLKIN_IBUFG_OUT : out   std_logic; 
          CLK0_OUT        : out   std_logic; 
          LOCKED_OUT      : out   std_logic);
end DCM71;

architecture BEHAVIORAL of DCM71 is
   signal CLKFB_IN        : std_logic;
   signal CLKFX_BUF       : std_logic;
   signal CLKIN_IBUFG     : std_logic;
   signal CLK0_BUF        : std_logic;
   signal GND_BIT         : std_logic;
begin
   GND_BIT <= '0';
   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
   CLK0_OUT <= CLKFB_IN;

   
   CLKFX_BUFG_INST : BUFG
      port map (I=>CLKFX_BUF,
                O=>CLKFX_OUT);

   
   CLKIN_IBUFG_INST : IBUFG
      port map (I=>CLKIN_IN,
                O=>CLKIN_IBUFG);
   
   CLK0_BUFG_INST : BUFG
      port map (I=>CLK0_BUF,
                O=>CLKFB_IN);
   
   DCM_SP_INST : DCM_SP
   generic map( CLK_FEEDBACK => "1X",
            CLKDV_DIVIDE => 2.0,
            CLKFX_DIVIDE => 7,
            CLKFX_MULTIPLY => 25,
            CLKIN_DIVIDE_BY_2 => FALSE,
            CLKIN_PERIOD => 50.000,
            CLKOUT_PHASE_SHIFT => "NONE",
            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
            DFS_FREQUENCY_MODE => "LOW",
            DLL_FREQUENCY_MODE => "LOW",
            DUTY_CYCLE_CORRECTION => TRUE,
            FACTORY_JF => x"C080",
            PHASE_SHIFT => 0,
            STARTUP_WAIT => FALSE)
      port map (CLKFB=>CLKFB_IN,
                CLKIN=>CLKIN_IBUFG,
                DSSEN=>GND_BIT,
                PSCLK=>GND_BIT,
                PSEN=>GND_BIT,
                PSINCDEC=>GND_BIT,
                --RST=>RST_IN,
					 RST=>GND_BIT,
                CLKDV=>open,
                CLKFX=>CLKFX_BUF,
                CLKFX180=>open,
                CLK0=>CLK0_BUF,
                CLK2X=>open,
                CLK2X180=>open,
                CLK90=>open,
                CLK180=>open,
                CLK270=>open,
                LOCKED=>LOCKED_OUT,
                PSDONE=>open,
                STATUS=>open);
   
end BEHAVIORAL;

And the contraints.ucf file:

# Crystal Clock - use 32MHz onboard oscillator
NET "clk_in" LOC = "P89" | IOSTANDARD = LVCMOS25 | PERIOD = 31.25ns ;

# Wing1 Column A
NET "LED1" LOC = "P91";	
NET "LED2" LOC = "P92";