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Jump to navigationJump to search- 11:45, 8 June 2013 diff hist +99 FPGA Test Board →Components
- 12:46, 7 June 2013 diff hist +232 FPGA Test Board →Components
- 10:16, 7 June 2013 diff hist +240 FPGA Test Board →Components
- 22:03, 6 June 2013 diff hist +203 N File:Bscan s3 spi isf-reset.vhdl bscan.vhdl to program Flash via xc3s500E (and others?) FPGA's. Changes: * resets 'header' signal after setting have_header<='0' * changes to make my Xilinx ISE 14.5 accept it (mostly remove SPI_ACCESS) current
- 23:22, 5 June 2013 diff hist +13 FPGA Test Board →Components
- 23:21, 5 June 2013 diff hist +2 FPGA Test Board →Components
- 23:20, 5 June 2013 diff hist +277 FPGA Test Board →Components
- 23:08, 5 June 2013 diff hist +234 FPGA Test Board →Components
- 20:34, 5 June 2013 diff hist +17 FPGA Test Board →Components
- 20:32, 5 June 2013 diff hist +233 FPGA Test Board →Components
- 20:07, 5 June 2013 diff hist +229 FPGA Test Board →Components
- 18:32, 5 June 2013 diff hist +20 FPGA Test Board →Components
- 17:37, 5 June 2013 diff hist -6 FPGA Test Board →Components
- 23:19, 4 June 2013 diff hist +363 FPGA Test Board →Components
- 21:13, 4 June 2013 diff hist -125 FPGA Test Board →Components
- 20:14, 4 June 2013 diff hist +11 FPGA Test Board →Components
- 18:16, 4 June 2013 diff hist +318 FPGA Test Board →Components
- 22:05, 3 June 2013 diff hist -241 Xc3sprog →xc3sprog & papilio
- 16:49, 1 June 2013 diff hist +1 VHDL →Projects on this site current
- 16:49, 1 June 2013 diff hist +5 VHDL →Projects on this site
- 16:49, 1 June 2013 diff hist +114 VHDL
- 08:52, 30 May 2013 diff hist +88 Papilio
- 23:56, 29 May 2013 diff hist -14 Xc3sprog →xc3sprog bscan 59a6 bug
- 23:25, 29 May 2013 diff hist -18 Xc3sprog →xc3sprog & papilio
- 23:24, 29 May 2013 diff hist +501 Xc3sprog →xc3sprog bscan 59a6 bug
- 23:24, 29 May 2013 diff hist +96 N File:Xc3s500e godil-59a3.bit bit file built using Bscan_s3_spi_isf.vhdl, works for XC3S500E (papilio), with 59 a6 59 a3 magic current
- 23:17, 29 May 2013 diff hist +138 Xc3sprog →xc3sprog bscan 59a6 bug
- 23:16, 29 May 2013 diff hist 0 N File:Bscan s3 spi isf.vhdl current
- 23:14, 29 May 2013 diff hist +559 Xc3sprog →xc3sprog bscan 59a6 bug
- 23:08, 29 May 2013 diff hist +261 Xc3sprog →xc3sprog bscan 59a6 bug
- 23:04, 29 May 2013 diff hist -4 Xc3sprog →xc3sprog bscan 59a6 bug
- 23:04, 29 May 2013 diff hist -124 Xc3sprog →xc3sprog bscan 59a6 bug
- 23:03, 29 May 2013 diff hist +1,847 Xc3sprog
- 22:31, 29 May 2013 diff hist +581 Xc3sprog →xc3sprog & papilio
- 22:20, 29 May 2013 diff hist +227 N Xc3sprog Created page with "=xc3sprog & papilio= The original xc3sprog doesn't support the SST flash on the Papilio. So instead use the papilio xc3sprog fork. Another option is to apply [http://tech.komputi…"
- 22:19, 29 May 2013 diff hist +53 N File:Xc3sprog-sst.diff backport of papilio patches to support the SST flash. current
- 23:27, 27 May 2013 diff hist +68 FPGA Clock/Trigger generator →Available Lines current
- 23:18, 27 May 2013 diff hist +331 FPGA Clock/Trigger generator →Measurements
- 17:49, 26 May 2013 diff hist +120 DCM module VHDL code current
- 22:58, 23 May 2013 diff hist +132 Xilinx →ISE WebPACK for Linux notes
- 12:53, 23 May 2013 diff hist 0 Xilinx →Issues (14.4)
- 12:52, 23 May 2013 diff hist -1 Xilinx →Issues (14.4)
- 08:18, 22 May 2013 diff hist 0 FPGA Clock/Trigger generator
- 19:52, 21 May 2013 diff hist +53 FPGA Clock/Trigger generator
- 14:38, 21 May 2013 diff hist +156 FPGA Clock/Trigger generator →Available Lines
- 13:32, 21 May 2013 diff hist -1 FPGA Clock/Trigger generator →Xilinx code to drive Differential signals
- 13:28, 21 May 2013 diff hist +47 FPGA Clock/Trigger generator →Measurements
- 13:26, 21 May 2013 diff hist +140 FPGA Clock/Trigger generator →differential signals
- 13:13, 21 May 2013 diff hist +53 FPGA Clock/Trigger generator →Xilinx code to drive Differential signals
- 12:57, 21 May 2013 diff hist +33 FPGA Clock/Trigger generator
